Integrated circuits are often formed using an application specific integrated circuit architecture, which tends to reduce the design costs of the integrated circuit by using predetermined logic blocks in a somewhat customized arrangement to produce an integrated circuit according to a customer's specifications. One aspect of such a customizable integrated circuit design is referred to as RRAM.
RRAM (Reconfigurable RAM) contains sets of memories of the same type that are placed compactly within a memory matrix. RRAM also contains sets of embedded tools that are used for mapping arbitrary logical customer memory designs to the physical memories in the matrix. All RRAM memory ports are ports of the customer memories. Ports of memories from the matrix are invisible from the outside of the RRAM. So from the customer's point of view, the RRAM is the set of the customer's memories.
The current strategy of testing the memory matrices is to test every memory of every matrix separately. That testing strategy requires additional ports to the RRAM, especially for all the ports of physical memories. On the other hand, it would be better to prepare different, non-trivial test-vectors for testing every memory.
What is needed, therefore, is an RRAM subsystem that overcomes problems such as those described above, at least in part.
As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, InP, or mixtures of such materials. The term includes all types of devices formed, such as memory, and all designs of such devices, such as MOS and bipolar.